FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 27

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and
result status are transferred between the host
processor and the floppy disk controller through
the Data Register.
Data transfers are governed by the RQM and DIO
bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode
after any form of reset.
hardware compatibility. The default values can be
changed through the Configure command (enable
full FIFO operation with threshold control). The
advantage of the FIFO is that it allows the system
a larger DMA latency without causing a disk error.
with
Table 14 gives several examples of the delays
FIFO THRESHOLD
FIFO THRESHOLD
FIFO THRESHOLD
EXAMPLES
EXAMPLES
EXAMPLES
This maintains PC/AT
15 bytes
15 bytes
15 bytes
*The 2 Mbps data rate is only available if V
2 bytes
8 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
1 byte
Table 12 - FIFO Service Delay
1 x 4 μs - 1.5 μs = 2.5 μs
2 x 4 μs - 1.5 μs = 6.5 μs
8 x 4 μs - 1.5 μs = 30.5 μs
15 x 4 μs - 1.5 μs = 58.5 μs
1 x 8 μs - 1.5 μs = 6.5 μs
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
1 x 16 μs - 1.5 μs = 14.5 μs
2 x 16 μs - 1.5 μs = 30.5 μs
8 x 16 μs - 1.5 μs = 126.5 μs
15 x 16 μs - 1.5 μs = 238.5 μs
MAXIMUM DELAY TO SERVICING AT 2
MAXIMUM DELAY TO SERVICING AT 1
MAXIMUM DELAY TO SERVICING AT
27
aFIFO.
formula:
At the start of a command, the FIFO action is
always disabled and command parameters must
be sent based upon the RQM and DIO bit settings.
FIFO is cleared of any data to ensure that invalid
data is not transferred.
An overrun or underrun will terminate the current
command and the transfer of data. Disk writes will
complete the current sector by generating a 00
pattern and valid CRC. Reads require the host to
remove the remaining data so that the result
phase may be entered.
500 Kbps DATA RATE
As the command execution phase is entered, the
Threshold # x
Mbps* DATA RATE
Mbps DATA RATE
The data is based upon the following
CC
DATA RATE
= 5V.
1
x 8
- 1.5 μs = DELAY