FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 26

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller. The
Main Status Register can be read at any
BIT 0 - 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek
portion of a command, including implied and
overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress. This bit will go active after the command
byte has been accepted and goes inactive at the
end of the results phase.
phase (Seek, Recalibrate commands), this bit is
returned to a 0 after the last command byte.
*The 2Mbps data rate
RQM
7
DIO
6
If there is no result
Table 11 - Default Precompensation Delays
DATA RATE
NON
DMA
500 Kbps
300 Kbps
250 Kbps
2 Mbps*
5
1 Mbps
BUSY
CMD
4
5V.
26
PRECOMPENSATION
Reserved Reserved
time. The MSR indicates when the disk controller
is ready to receive data via the Data Register. It
should be read before each byte transferring to or
from the data register except in DMA mode. No
delay is required when reading the MSR after a
data transfer.
BIT 5 NON-DMA
This mode is selected in the SPECIFY command
and will be set to a 1 during the execution phase of
a command. This is for polled data transfers and
helps differentiate between the data transfer phase
and the reading of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set. A 1 indicates a read and a 0 indicates
a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a
1. No access is permitted if set to a 0.
3
DELAYS
41.67 ns
20.8 ns
125 ns
125 ns
125 ns
2
DRV1
BUSY
1
is only available if V
DRV0
BUSY
0
CC
=