FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 89

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

EPP 1.7 Read
The timing for a read operation (data) is shown in
timing diagram EPP 1.7 Read Data cycle.
89
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be used
to extend the cycle time.
complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
The host sets PDIR bit in the control register
to a logic "1". This deasserts nWRITE and tri-
states the PData bus.
The host selects an EPP register and drives
nIOR active.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR is
set and the nWRITE signal is valid.
If
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may begin the
termination phase of the cycle.
When the host deasserts nIOR the chip
deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
nWAIT
is
asserted,
The read cycle can
IOCHRDY
is