EM638165 Etron Technology Inc., EM638165 Datasheet - Page 10

• Manufacturer Part Number: EM638165
• Description: 4Mega x 16 Synchronous DRAM (SDRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
7
8
CLK
DQM
COMM AND
ADDRESS
DQ
CLK
COMMAND
CAS# latency=2
t CK2 , DQ's
CAS# latency=3
t CK3 , DQ's
: don't care
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals t
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",
A0-A7 = Column Address)
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + t
performed in this command and the auto precharge function is ignored.
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as all banks are in the idle
state.
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
The Write and AutoPrecharge command performs the precharge operation automatically after
The mode register stores the data for controlling the various operating modes of SDRAM. The
Burst Write with Auto-Precharge
t
DAL
Activate
=
Bank A
T0
t
WR
BA NK
COL n
WRITE
DIN
T0
n
+
t
RP
T 1
NOP
NOP
DIN
n + 1
T 1
t WR
NOP
T2
WR
BANK (S)
Precharge
/t
T2
CK
Write to Precharge
WR
rounded up to the next whole number. In addition, the DQM
AutoPrecharge
DIN A 0
DIN A 0
Write A
+ t
T3
RP
10
NOP
(min.)}. At full-page burst, only the write operation is
T3
(Burst Length = 2, CAS# Latency = 2, 3)
DIN A 1
DIN A 1
NOP
T4
t RP
NOP
T4
*
*
T5
*
NOP
Begin AutoPrecharge
Bank can be reactivated at completion of
t
DAL
Activate
ROW
T5
T6
NOP
t
DAL
Rev 0.6
EM638165
NOP
T6
T7
NOP
t
DAL
Feb. 2001
NOP
T8