EM638165 Etron Technology Inc., EM638165 Datasheet - Page 9

• Manufacturer Part Number: EM638165
• Description: 4Mega x 16 Synchronous DRAM (SDRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
6
CLK
COM MAND
DQ0 - DQ3
CLK
COMMAND
DQ's
CLK
COMMAND
CAS# latency=2
t CK2 , DQ's
CAS# latency=3
t CK3 , DQ's
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address)
row in an active bank. The bank must be active for at least t
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
The Write command is used to write a burst of data on consecutive clock cycles from an active
A write burst without the auto precharge function may be interrupted by a subsequent Write,
The Read command that interrupts a write burst without auto precharge function should be
Write Interrupted by a Write
The first data element and the write
are registered on the same clock edge.
Write Interrupted by a Read
T0
T0
T0
NOP
NOP
Burst Write Operation
NOP
Input data for the write is masked.
WRITE A
DIN A 0
WRITE A
WRITE A
DIN A 0
T 1
T 1
DIN A 0
T 1
DIN A 0
1 Clk Interval
WRITE B
READ B
DIN B 0
don't care
don't care
DIN A 1
T2
T2
T2
NOP
(Burst Length = 4, CAS# Latency = 1, 2, 3)
DIN B 1
DIN A 2
don't care
T3
T3
NOP
T3
NOP
NOP
(Burst Length = 4, CAS# Latency = 1, 2, 3)
(Burst Length = 4, CAS# Latency = 2, 3)
9
DIN B 2
DIN A 3
T4
NOP
NOP
T4
T4
NOP
DOUT B 0
Extra data is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DIN B 3
don't care
RCD
T5
NOP
T5
T5
NOP
NOP
DOUT B 0
DOUT B 1
(min.) before the Write command is
T6
NOP
T6
NOP
T6
NOP
DOUT B 2
DOUT B 1
Rev 0.6
EM638165
T7
NOP
DOUT B 3
T7
NOP
T7
NOP
DOUT B 2
Feb. 2001
NOP
T8
NOP
NOP
DOUT B 3
T8
T8