EM638165 Etron Technology Inc., EM638165 Datasheet - Page 18

• Manufacturer Part Number: EM638165
• Description: 4Mega x 16 Synchronous DRAM (SDRAM)
• Manufacturer: Etron Technology Inc.

6. A.C. Test Conditions
LVTTL Interface
7. Transition times are measured between V
8. t
9. If clock rising time is longer than 1 ns, ( t
10. Assumed input rise and fall time t
11. Power up Sequence
Preliminary
Transition Time (Rise and Fall) of Input Signals
Output
fixed slope (1 ns).
levels.
If t
should be added to the parameter.
HZ
Power up must be performed in the following sequence.
1) Power must be applied to V
2) After power-up, a pause of 200 seconds minimum is required. Then, it is recommended that DQM
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
LVTTL D.C. Test Load (A)
R
defines the time in which the outputs achieve the open circuit condition and are not at reference
Reference Level of Output Signals
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
is held "HIGH" (V
the device.
or t
Reference Level of Input Signals
F
is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
Input Signal Levels
30pF
Output Load
DD
levels) to ensure DQ output is in high impedance.
1.2k
3.3V
87 0
DD
T
and V
( t
R
& t
DDQ
R
F
/ 2 -0.5) ns should be added to the parameter.
IH
) = 1 ns
(simultaneously) when all input signals are held "NOP" state
Output
and V
18
LVTTL A.C. Test Load (B)
IL
Reference to the Under Output Load (B)
. Transition(rise and fall) of input signals are in a
Z0=
50
1.4V / 1.4V
2.4V / 0.4V
1.4V
1ns
30pF
5 0
1.4V
Rev 0.6
EM638165
Feb. 2001