EM638165 Etron Technology Inc., EM638165 Datasheet - Page 6

• Manufacturer Part Number: EM638165
• Description: 4Mega x 16 Synchronous DRAM (SDRAM)
• Manufacturer: Etron Technology Inc.

Commands
Preliminary
1
2
3
4
CLK
ADDRESS
COM MAND
: "H" or "L"
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
latching the row address on A0 to A11 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of t
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by t
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of the four banks. t
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
bank is switched from the active state to the idle state. This command can be asserted anytime after
t
bank can be active is specified by t
in any active bank within t
state and is ready to be activated again.
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0 -A9 and A11 = Don't care)
banks are not in the active state. All banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)
row in an active bank. The bank must be active for at least t
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
RAS
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
The BankActivate command activates the idle bank designated by the BA0,1 signals. By
The BankPrecharge command precharges the bank disignated by BA signal. The precharged
The PrechargeAll command precharges all banks simultaneously and can be issued even if all
The Read command is used to read a burst of data on consecutive clock cycles from an active
BankActivate Command Cycle
Row Addr.
Activate
Bank A
Bank A
T0
RAS# - CAS# delay (
T 1
NOP
RAS
RC
(max.). At the end of precharge, the precharged bank is still in the idle
(min.). The SDRAM has four internal banks on the same chip and
T2
NOP
RRD
t
RCD
(min.) specifies the minimum time required between activating
)
RAS
(max.). Therefore, the precharge function must be performed
AutoPrecharge
Col Addr.
T3
R/W A with
Bank A
RAS# Cycle time (
6
(Burst Length = n, CAS# Latency = 3)
..............
..............
..............
t
RC
)
AutoPrecharge
Row Addr.
Tn+3
Activate
Begin
Bank B
Bank B
RCD
(min.) before the Read command is
RAS# - RAS# delay time (
Tn+4
NOP
Rev 0.6
EM638165
Tn+5
NOP
t
RRD
)
Feb. 2001
Row Addr.
Activate
RCD
Bank A
Bank A
Tn+6
(min.)