XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 119

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

DC and Switching Characteristics
Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
16
Notes:
1.
2.
3.
Hold Times
T
T
T
Clock Timing
T
T
F
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
Symbol
The numbers in this table are based on the operating conditions set forth in
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
The time from the rising transition at the CCLK pin to the point when data is
last held at the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
With bitstream compression
Description
www.xilinx.com
Not using the BUSY pin
Using the BUSY pin
Table
4.
(2)
Advance Product Specification
All Speed Grades
DS312-3 (v1.0) March 1, 2005
Min
5
0
0
0
5
-
-
-
Max
50
66
20
-
-
-
-
-
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
R