XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 157

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Pinout Descriptions
User I/Os by Bank
Table
user-I/O pins are distributed between the four I/O banks on
the FT256 package.
Table 20: User I/Os Per Bank on XC3S250E in the FT256 Package
Table 21: User I/Os Per Bank on XC3S500E in the FT256 Package
Table 22: User I/Os Per Bank on XC3S1200E in the FT256 Package
36
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Package
Edge
Edge
Edge
20,
Table
21, and
I/O Bank
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
0
1
2
3
Table 22
indicate how the available
Maximum
Maximum
Maximum
172
190
190
I/O
I/O
I/O
44
42
44
42
46
48
48
48
46
48
48
48
I/O
I/O
I/O
20
10
24
62
22
15
11
28
76
24
14
13
27
78
8
www.xilinx.com
The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond ( ) symbol in
Figure
INPUT
INPUT
INPUT
10
33
10
33
31
7
9
7
7
9
7
8
8
7
8
All Possible I/O Pins by Type
All Possible I/O Pins by Type
All Possible I/O Pins by Type
7.
DUAL
DUAL
DUAL
21
24
46
21
24
46
21
24
46
1
0
1
0
1
0
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
VREF
VREF
VREF
15
19
19
5
4
3
3
5
5
4
5
5
5
4
5
GCLK
GCLK
GCLK
16
16
16
8
0
0
8
8
0
0
8
8
0
0
8
R