XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 56
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XC3S250E
Manufacturer Part Number
XC3S250E
Description
Spartan-3E FPGA Family
Manufacturer
Xilinx, Inc.
Datasheet
1.XC3S250E.pdf
(193 pages)
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BUFGMUX pair connects to four of the eight global clock
inputs, as shown in
ential inputs to the global clock inputs without wasting a
BUFGMUX element.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Notes:
1.
2.
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
BUFGMUX
Number of DCMs and locations of these DCM varies for different device densities.
The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right
and one on the bottom right of the die.
BUFGMUX
DCM
DCM
pair
R
4
4
4
4
4
4
4
4
H
G
E
C
B
A
F
D
Figure
Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View)
Top Left Quadrant (TL)
Left Spine
Bottom Left Quadrant (BL)
42. This optionally allows differ-
XC3S1200E (X1Y3)
XC3S1600E (X1Y3)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S250E (X0Y0)
XC3S500E (X0Y0)
DCM
DCM
8
Figure 44a
Figure 44a
•
•
•
•
•
•
8
8
4
4
4
8
4
GCLK11
GCLK2
X1Y10 X1Y11
X1Y0 X1Y1
GCLK10
GCLK3
Global Clock Inputs
D
H
Horizontal
GCLK14
Global Clock Inputs
GCLK7
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GCLK15
GCLK6
G
C
4
GCLK0
GCLK9
4
X2Y10 X2Y11
X2Y0 X2Y1
GCLK8
GCLK1
The connections for the bottom-edge BUFGMUX elements
is similar to the top-edge connections.
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
B
F
Spine
GCLK12
GCLK5
GCLK13
GCLK4
A
E
4
4
8
4
4
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
Bottom Right Quadrant (BR)
Figure 44b
Figure 44b
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
Top Right Quadrant (TR)
•
•
•
•
•
•
8
8
DCM
DCM
8
Right Spine
Functional Description
in Quadrant
Clock Line
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
4
4
4
4
H
G
E
C
B
A
F
D
DS312-2_04_030205
4
4
4
4
DCM
DCM
49