XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 76

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

SPI Flash PROM Density Requirements
Table 49
program a single Spartan-3E FPGA. Commercially avail-
able SPI Flash PROMs range in density from 1 Mbit to 128
Mbits. A multiple-FPGA daisy-chained application requires
a SPI Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-den-
sity SPI Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the SPI Flash
PROM can also store application code for a MicroBlaze™
RISC processor core integrated in the Spartan-3E FPGA.
See
Table 49: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock input
pin. The FPGA starts configuration at its lowest frequency
and increases its frequency for the remainder of the config-
uration process if so specified in the configuration bitstream.
The maximum frequency is specified using the ConfigRate
bitstream generator option. The maximum frequency sup-
ported by the FPGA configuration logic depends on the tim-
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
Using the SPI Flash Interface after
Device
shows the smallest usable SPI Flash PROM to
R
Configuration
Number of
1,352,192
2,267,136
3,832,320
5,957,760
581,344
Bits
SPI Flash PROM
Smallest Usable
Configuration.
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
www.xilinx.com
ing for the SPI Flash device. Without examining the timing
for a specific SPI Flash PROM, use ConfigRate = 12,
which is approximately 12 MHz. SPI Flash PROMs that sup-
port the FAST READ command support higher data rates.
Some such PROMs support up to ConfigRate = 25 and
beyond but require careful data sheet analysis.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Because all the interface pins are user I/O after configura-
tion, the FPGA application can continue to use the SPI
Flash interface pins to communicate with the SPI Flash
PROM, as shown in
dom-accessible, byte-addressable, read/write, non-volatile
storage to the FPGA application.
SPI Flash PROMs are available in densities ranging from
1 Mbit up to 128 Mbits. However, a single Spartan-3E FPGA
requires less than 6 Mbits. If desired, use a larger SPI Flash
PROM to contain additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. In the example
shown in
PROM. Then using FPGA logic after configuration, the
FPGA copies MicroBlaze code from SPI Flash into external
DDR SDRAM for code execution. Similarly, the FPGA appli-
cation can store non-volatile application data within the SPI
Flash PROM.
The FPGA configuration data is stored starting at location 0.
Store any additional data beginning in the next available SPI
Flash PROM sector or page. Do not mix configuration data
and user data in the same sector or page.
Figure
53, the FPGA configures from SPI Flash
Figure
53. SPI Flash PROMs offer ran-
Functional Description
69