XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 36

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Block RAM Port Signal Definitions
Representations
RAMB16_S[w
RAMB16_S[w] with their associated signals are shown in
Figure 29a
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
and
R
512x36
A
]_S[w
Figure
B
of
]
29b, respectively. These signals are
P3
35
and
Parity
P2
34
the
P1
33
the
P0
32
31
dual-port
single-port
Byte 3
24
primitive
primitive
1Kx18
23
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Byte 2
17
P3
P1
defined in
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
16
P2
P0
Data
16
15
15
2Kx9
Table
Byte 1
Byte 3
Byte 1
20. The control signals (WE, EN, CLK, and
P3
P2
P1
P0
8
8
8
4Kx4
7
7
7
8Kx2
16Kx1
Byte 3
Byte 2
Byte 1
Byte 0
Byte 0
Byte 2
Byte 0
7
3
3
7
3
DS312-2_02_020705
6
2
2
6
2
5
1
7
5
3
1
7
5
3
1
1
5
1
1
Functional Description
6
4
2
6
4
2
0
4
0
4
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
Address
1F
1E
1D
1C
0
1
0
3
2
1
0
7
6
1
0
F
E
D
C
3
2
1
0
3
2
1
0
29