XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 20

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Configurable Logic Block (CLB) and
Slice Resources
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to imple-
ment logic and two dedicated storage elements that can be
used as flip-flops or latches. The LUTs can be used as a
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
Table 6: Spartan-3E CLB Resources
Slices
Each CLB comprises four interconnected slices, as shown
in
organized as a column with an independent carry chain.
The left pair supports both logic and memory functions and
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Notes:
1.
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Figure
Device
The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see
13. These slices are grouped in pairs. Each pair is
R
Rows
CLB
22
34
46
60
76
Columns
Module
CLB
16
26
34
46
58
Spartan-3E
FPGA
1, Figure 1).
Total
1164
2168
3688
CLB
240
612
(1)
Figure 11: CLB Locations
Slices
14752
2448
4656
8672
960
www.xilinx.com
CLB
Flip-Flops
X0Y3
X0Y2
X0Y1
X0Y0
and additional multiplexers and carry logic simplify wide
logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
CLB Array
The CLBs are arranged in a regular array of rows and col-
umns as shown in
Each density varies by the number of rows and columns of
CLBs (see
LUTs support both logic and memory (including both
RAM16 and SRL16 shift registers) while half support logic
only, and the two types alternate throughout the array col-
umns. The SLICEL reduces the size of the CLB and lowers
the cost of the device, and can also provide a performance
advantage over the SLICEM.
LUTs /
17344
29504
1920
4896
9312
Slice
X1Y3
X1Y2
X1Y1
X1Y0
Table
IOBs
Logic Cells
X2Y3
X2Y2
X2Y1
X2Y0
Equivalent
10476
19512
33192
6).
2160
5508
Figure
X3Y3
X3Y2
X3Y1
X3Y0
DS312-2_31_021205
11.
RAM16 /
SRL16
14752
2448
4656
8672
960
Functional Description
Distributed
RAM Bits
138752
236032
15360
39168
74496
13