XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 12

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Spartan-II CLB
supports two separate carry chains, one per slice. The
height of the carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Spartan-II CLB contains two 3-state drivers (BUFTs)
that can drive on-chip busses. See
page
control pin and an independent input pin.
Block RAM
Spartan-II FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory struc-
tures implemented in CLBs.
Block RAM memory blocks are organized in columns. All
Spartan-II devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and conse-
quently, a Spartan-II device eight CLBs high will contain two
memory blocks per column, and a total of four blocks.
Table 4: Spartan-II Block RAM Amounts
Each block RAM cell, as illustrated in
chronous dual-ported 4096-bit RAM with independent con-
trol signals for each port. The data widths of the two ports
can
bus-width conversion.
DS001-2 (v2.2) September 3, 2003
Product Specification
Spartan-II
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
6. Each Spartan-II BUFT has an independent 3-state
be
configured
R
# of Blocks
independently,
10
12
14
4
6
8
Figure
Dedicated Routing,
Total Block RAM
providing
4, is a fully syn-
Bits
16K
24K
32K
40K
48K
56K
built-in
www.xilinx.com
1-800-255-7778
Table 5
block RAM.
Table 5: Block RAM Port Aspect Ratios
The Spartan-II block RAM also includes dedicated routing
to provide an efficient interface with both CLBs and other
block RAMs.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Spartan-II routing
architecture and its place-and-route software were defined
in a single optimization process. This joint optimization min-
imizes long-path delays, and consequently, yields the best
system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Local Routing
The local routing resources, as shown in
the following three types of connections:
•
•
Width
Spartan-II 2.5V FPGA Family: Functional Description
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM)
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
16
1
2
4
8
shows the depth and width aspect ratios for the
Figure 4: Dual-Port Block RAM
WEA
ENA
RSTA
ADD[#:0]
DIA[#:0]
WEB
ENB
RSTB
ADDRB[#:0]
DIB[#:0]
Depth
CLKA
CLKB
4096
2048
1024
512
256
RAMB4_S#_S#
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
ADDR Bus
DOA[#:0]
DOB[#:0]
Figure
DS001_05_060100
DATA<15:0>
DATA<1:0>
DATA<3:0>
DATA<7:0>
Data Bus
DATA<0>
Module 2 of 4
5, provide
5