XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 8

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

DS001-2 (v2.2) September 3, 2003
Architectural Description
Spartan-II Array
The Spartan-II user-programmable gate array, shown in
Figure
•
•
•
•
•
As can be seen in
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
DS001-2 (v2.2) September 3, 2003
Product Specification
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
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1, is composed of five major configurable elements:
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Figure
TFF
OFF
IFF
1, the CLBs form the central logic
R
Figure 1: Spartan-II Input/Output Block (IOB)
046
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Spartan-II 2.5V FPGA Family:
Functional Description
Product Specification
Values stored in static memory cells control all the config-
urable logic elements and interconnect resources. These
values load into the memory cells on power-up, and can
reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the fol-
lowing sections.
Input/Output Block
The Spartan-II IOB, as seen in
outputs that support a wide variety of I/O signaling stan-
dards. These high-speed inputs and outputs are capable of
supporting various state of the art memory and bus inter-
faces.
ported along with the required reference, output and
termination voltages needed to meet the standard.
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
Table 1
lists several of the standards which are sup-
Figure
1, features inputs and
Module 2 of 4
1