XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 24

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Multiple Spartan-II FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simulta-
neously. To configure multiple devices in this way, wire the
individual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See
page
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 18, page 18
used to load data into the Spartan-II FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 10, page
in
DS001-2 (v2.2) September 3, 2003
Product Specification
Figure 19, page
13.
DONE
INIT
PROGRAM
DATA[7:0]
CCLK
WRITE
BUSY
R
12. The timing for write operations is shown
19.
shows a flowchart of the write sequence
330Ω
CS(0)
Figure 17: Slave Parallel Configuration Circuit Diagram
2.5V
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
M1 M2
Start-up,
Spartan-II
FPGA
GND
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INIT
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or de-asserted. Otherwise an abort
will be initiated, as in the next section.
1. Drive data onto D0-D7. Note that to avoid contention,
2. On the rising edge of CCLK: If BUSY is Low, the data is
3. Repeat steps 1 and 2 until all the data has been sent.
4. De-assert CS and WRITE.
Spartan-II 2.5V FPGA Family: Functional Description
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
CS(1)
2.5V
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
M1 M2
Spartan-II
FPGA
GND
INIT
DS001_18_102401
Module 2 of 4
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