XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 58

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
DS001-3 (v2.7) September 3, 2003
Product Specification
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
4.
T
T
PSDLL
PSFD
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DLL output jitter is already included in the timing calculation.
A zero hold time listing indicates no hold time or a negative hold time.
For data input with different standards, adjust the setup time delay by the values shown in
Different Standards, page
Standard Global Clock Input Adjustments, page
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
A zero hold time listing indicates no hold time or a negative hold time.
For data input with different standards, adjust the setup time delay by the values shown in
Different Standards, page
Standard Global Clock Input Adjustments, page
Symbol
Symbol
/ T
/ T
R
PHDLL
PHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,
with DLL
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,
without DLL
7. For a global clock input with standards other than LVTTL, adjust delays with values from the
7. For a global clock input with standards other than LVTTL, adjust delays with values from the
Description
Description
11.
11.
(1)
(1)
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Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
Device
All
1.7 / 0
IOB Input Delay Adjustments for
2.2 / 0
2.2 / 0
2.2 / 0
2.3 / 0
2.4 / 0
2.4 / 0
IOB Input Delay Adjustments for
Min
Min
-6
-6
Speed Grade
Speed Grade
1.9 / 0
2.7 / 0
2.7 / 0
2.7 / 0
2.8 / 0
2.9 / 0
3.0 / 0
Min
Min
-5
-5
Module 3 of 4
Units
Units
I/O
I/O
ns
ns
ns
ns
ns
ns
ns
5