XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 21

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
default timing for start-up is shown in the top half of
Figure
any CCLK cycle C1-C6 through settings in the Xilinx
Development Software. Heavy lines show default settings.
The bottom half of
used
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
Module 2 of 4
14
Start-up CLK
Start-up CLK
12. The four operations can be selected to switch on
version
DONE
DONE
Phase
Phase
Figure 12: Start-Up Waveforms
GWE
GWE
GSR
GSR
GTS
GTS
of
Figure 12
the
DONE High
0
0
1
1
Default Cycles
Sync to DONE
start-up
2
2
shows another commonly
3
3
4
4
timing
5
5
DS001_13_090600
6 7
6 7
known
www.xilinx.com
1-800-255-7778
as
Serial Modes
There are two serial configuration modes: In Master Serial
mode, the FPGA controls the configuration process by driv-
ing CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per CCLK
cycle. The MSB of each configuration data byte is always
written to the DIN pin first.
See
Spartan-II FPGA serially. This is an expansion of the "Load
Configuration Data Frames" block in
CS and WRITE normally are not used during serial configu-
ration. To ensure successful loading of the FPGA, do not
toggle WRITE with CS Low during serial configuration.
Slave Serial Mode
In Slave Serial mode, the FPGA’s CCLK pin is driven by an
external source, allowing FPGAs to be configured from
other logic devices such as microprocessors or in a
daisy-chain configuration.
a Master Serial FPGA configuring a Slave Serial FPGA
from a PROM. A Spartan-II device in slave serial mode
should be connected as shown for the third device from the
left. Slave Serial mode is selected by a <11x> on the mode
pins (M0, M1, M2).
Figure 15
The serial bitstream must be setup at the DIN input pin a
short time before each rising edge of an externally gener-
ated CCLK. Multiple FPGAs in Slave Serial mode can be
daisy-chained for configuration from a single source. After
an FPGA is configured, data for the next device is routed to
the DOUT pin. Data on the DOUT pin changes on the rising
edge of CCLK. Configuration must be delayed until INIT
pins of all daisy-chained FPGAs are High. For more infor-
mation, see
Figure 13: Loading Serial Mode Configuration Data
Figure 13
shows the timing for Slave Serial configuration.
Start-up, page
for the sequence for loading data into the
CCLK Rising Edge
To CRC Check
User Load One
Configuration
Configuration
Goes High
Bit on Next
After INIT
Data File?
End of
Figure 14
Yes
DS001-2 (v2.2) September 3, 2003
13.
No
DS001_14_042403
shows connections for
Product Specification
Figure
10. Note that
R