LM3S1133 Luminary Micro, Inc, LM3S1133 Datasheet - Page 253
LM3S1133
Manufacturer Part Number
LM3S1133
Description
Lm3s1133 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1133.pdf
(527 pages)
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Reset
Reset
Type
Type
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
July 26, 2008
Bit/Field
31:9
7:0
8
RO
RO
31
15
0
0
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
RO
RO
30
14
0
0
reserved
reserved
RO
RO
29
13
STALL
0
0
Name
reserved
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
RO
26
10
0
0
Reset
0x00
0x00
RO
RO
25
0
9
0
0
Preliminary
STALL
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Stall Enable
When set to 1, if the Stellaris
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
®
microcontroller is stopped with a
RO
RO
20
0
4
0
reserved
LM3S1133 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
253
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