LM3S1133 Luminary Micro, Inc, LM3S1133 Datasheet - Page 444
LM3S1133
Manufacturer Part Number
LM3S1133
Description
Lm3s1133 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1133.pdf
(527 pages)
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Reset
Reset
Type
Type
Pulse Width Modulator (PWM)
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
444
Bit/Field
31:6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. Bits set to 1 indicate the latched events that
have occurred; bits set to 0 indicate that the event in question has not occurred.
RO
RO
30
14
0
0
IntCntLoad
IntCntZero
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
reserved
RO
RO
29
13
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator B Down Interrupt Status
Indicates that the counter has matched the comparator B value while
counting down.
Comparator B Up Interrupt Status
Indicates that the counter has matched the comparator B value while
counting up.
Comparator A Down Interrupt Status
Indicates that the counter has matched the comparator A value while
counting down.
Comparator A Up Interrupt Status
Indicates that the counter has matched the comparator A value while
counting up.
Counter=Load Interrupt Status
Indicates that the counter has matched the PWMnLOAD register.
Counter=0 Interrupt Status
Indicates that the counter has matched 0.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
IntCmpBD
RO
RO
21
0
5
0
IntCmpBU
RO
RO
20
0
4
0
IntCmpAD
RO
RO
19
0
3
0
IntCmpAU
RO
RO
18
0
2
0
IntCntLoad
July 26, 2008
RO
RO
17
0
1
0
IntCntZero
RO
RO
16
0
0
0
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