LM3S1133 Luminary Micro, Inc, LM3S1133 Datasheet - Page 435
![no-image](/images/no-image-200.jpg)
LM3S1133
Manufacturer Part Number
LM3S1133
Description
Lm3s1133 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1133.pdf
(527 pages)
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Reset
Reset
Type
Type
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
July 26, 2008
Bit/Field
31:2
1
0
RO
RO
31
15
0
0
Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the
fault inputs and debug events are considered fault conditions. On a fault condition, each PWM signal
can be passed through unmodified or driven Low. For outputs that are configured for pass-through,
the debug event handling on the corresponding PWM generator also determines if the PWM signal
continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven Low on fault are
inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition).
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
Fault1
Fault0
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
0
reserved
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM1 Fault
When set, the PWM1 output signal is driven Low on a fault condition.
PWM0 Fault
When set, the PWM0 output signal is driven Low on a fault condition.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S1133 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
Fault1
R/W
RO
17
0
1
0
Fault0
R/W
RO
16
0
0
0
435
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