IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet

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IDT723642L15PF

Manufacturer Part Number
IDT723642L15PF
Description
IC FIFO SYNC 2048X36 120QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723642L15PF

Function
Synchronous
Memory Size
72K (2K x 36)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
36b
Organization
1Kx36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
400mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723642L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723642L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT723642L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
©
FEATURES:
• • • • •
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• • • • •
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
Memory storage capacity:
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Two independent clocked FIFOs buffering data in opposite
directions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
IRA, ORA, AEA, and AFA flags synchronized by CLKA
IRB, ORB, AEB, and AFB flags synchronized by CLKB
Supports clock frequencies up to 83MHz
Fast access times of 8ns
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT723622
IDT723632
IDT723642
A
MBF2
CLKA
0
W/RA
RST1
MBA
ORA
CSA
ENA
- A
AEA
– 256 x 36 x 2
– 512 x 36 x 2
– 1,024 x 36 x 2
AFA
FS
FS
IRA
35
0
1
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
36
36
CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
10
FIFO 1
FIFO 2
Pointer
Pointer
Read
Write
Programmable Flag
Offset Registers
Status Flag
Status Flag
1,024 x 36
1,024 x 36
256 x 36
512 x 36
256 x 36
512 x 36
Register
Register
ARRAY
ARRAY
Mail 1
Mail 2
Logic
Logic
RAM
RAM
1
• • • • •
• • • • •
• • • • •
• • • • •
DESCRIPTION:
CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre-
quencies up to 83MHz and have read access times as fast as 8ns. Two
independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip
buffer data in opposite directions. Communication between each port may
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored.
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-
saving 120-pin Thin Quad Flatpack (TQFP)
Low-power 0.8-Micron Advanced CMOS technology
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
Pointer
Pointer
The IDT723622/723632/723642 are a monolithic, high-speed, low-power,
These devices are a synchronous (clocked) FIFO, meaning each port
Read
Write
TM
36
36
Control
FIFO2,
Mail2
Reset
Logic
Port-B
Logic
FEBRUARY 2009
3022 drw 01
ORB
AEB
B
IRB
AFB
MBF1
0
RST2
CLKB
CSB
W/RB
ENB
MBB
- B
IDT723622
IDT723632
IDT723642
35
DSC-3022/5

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IDT723642L15PF Summary of contents

Page 1

FEATURES: • • • • • Memory storage capacity: IDT723622 – 256 IDT723632 – 512 IDT723642 – 1,024 • • • • • Free-running CLKA and CLKB may ...

Page 2

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 DESCRIPTION (CONTINUED) each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged ...

Page 3

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 PIN CONFIGURATION (CONTINUED ...

Page 4

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/0 AEA Port A Almost- O Empty Flag (Port A) AEB Port B ...

Page 5

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O ORA Output Ready O Flag (Port A) ORB Output Ready O Flag (Port B) RST1 FIFO1 ...

Page 6

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input Voltage Range ...

Page 7

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and ...

Page 8

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial ± 10 0°C to ...

Page 9

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial ± 10%, ...

Page 10

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 SIGNAL DESCRIPTION RESET After power up, a Master Reset operation must be performed by providing a LOW pulse to RSTI and RST2 ...

Page 11

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 The setup and hold time constraints to the port Clocks for the port Chip Selects and Write/Read selects are only for enabling ...

Page 12

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a ...

Page 13

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 ALMOST-FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. ...

Page 14

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLKA CLKB t RSTS RST1 FS1,FS0 IRA ORB t RSF AEB t RSF AFA t RSF MBF1 NOTE: 1. FIFO2 is reset ...

Page 15

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLK t t CLKH CLKL CLKA IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA t ...

Page 16

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLK t t CLKH CLKL CLKB ORB HIGH CSB W/RB t ENS2 MBB ENB t MDV B35 ...

Page 17

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLKA CSA LOW WRA HIGH t t ENS2 ENH MBA t ENS2 t ENH ENA IRA HIGH ...

Page 18

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLKB CSB LOW W/RB LOW t ENS2 t ENH MBB t t ENH ENS2 ENB IRB HIGH ...

Page 19

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0 -B35 Previous Word ...

Page 20

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW LOW MBA t ENS2 ENA ORA HIGH A0 -A35 Previous Word ...

Page 21

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLKB t t EN2S ENH ENB t SKEW2 CLKA AEA X2 Words in FIFO2 ENA NOTES: is the minimum time between a ...

Page 22

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLKB t t ENS2 ENB AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES: is the minimum time between a rising CLKB edge ...

Page 23

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB t DS B0-B35 CLKA MBF2 CSA W/RA MBA ENA ...

Page 24

IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 512 1,024 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND ...

Page 25

ORDERING INFORMATION XXXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range is available by special order. 2. Green parts are available. For specific speeds and packages please contact your sales office. DATASHEET DOCUMENT HISTORY 10/04/2000 pgs. 1 ...

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