IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 17

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

A0 - A35
B0 - B35
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTE:
1. t
If the time between the rising CLKA edge and rising CLKB edge is less than t
cycle later than shown.
CLKA
CLKB
W/RB
SKEW1
WRA
MBA
ORB
CSA
MBB
ENA
CSB
ENB
IRA
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
HIGH
FIFO1 Empty
LOW
HIGH
HIGH
LOW
LOW
t
t
ENS2
t
ENS2
DS
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty
W1
t
SKEW1
t
t
t
ENH
DH
ENH
Old Data in FIFO1 Output Register
(1)
t
CLKH
1
t
CLK
t
CLKL
SKEW1
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
17
2
t
CLKH
t
CLK
t
CLKL
t
POR
3
t
A
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
POR
t
ENH
W1
4660 drw 10