MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 16

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

MT90868
connected to the switch matrix cards. Each input
data stream can have its own input bit delay value
programmed by the input delay registers. The local
input delay registers (LIDR0 - LIDR21) are used to
program the local input delay. The backplane input
delay registers (BIDR0 - BIDR21) are used to
program the backplane input delay. See Tables 11,
12 and Tables 14, 15 for the descriptions of the LIDR
and BIDR registers.
16
Bit Advancement = -1 1/2
Bit Advancement = -1/2
Bit Advancement = -1/4
Bit Advancement = -1/2
Bit Advancement = -3/4
Bit Advancement = -1
Bit Advancement = 0
Bit advancement = 0
Figure 8 - Backplane Output Advancement Timing Diagram when the Data Rate is 16Mb/s
Figure 9 - Backplane Output Advancement Timing Diagram when the Data Rate is 32Mb/s
(32.768Mb/s)
(16.384Mb/s)
(Default)
(Default)
BSToX
BSToX
BSToX
BSToX
BSToX
BSToX
BSToX
BSToX
FP8i
FP8i
C8i
C8i
Bit 5
Bit 5
Bit 2
Bit 5
Bit 4
Ch511
Bit 2
Bit 5
Bit 4
Ch255
Ch511
Bit Advancement, -1 1/2
Bit 2
Bit 3
Bit 4
Ch255
Ch511
Bit Advancement, -3/4
Bit 2
Bit 3
Bit 4
Bit Advancement, -1
Ch255
Bit 1
Ch511
Bit Advancement, -1/2
Bit 2
Bit Advancement, -1/2
Bit 3
Ch255
Bit 1
Bit Advancement, -1/4
Bit 2
Bit 3
Bit 1
Bit 1
Bit 2
Bit 1
Bit 1
Bit 2
Bit 0
Bit 0
Bit 1
Bit 0
Bit 0
Bit 1
Bit 0
Bit 0
Bit 7 Bit 6
Possible adjustment of the local input data streams,
LSTi0 - LSTi63 is up to 7 3/4 bits. The resolution is
1/4 bit or 1/4 C8o cycle. For backplane, the possible
adjustment of the input data streams, BSTi0 -
BSTi63 is up to 7 3/4 bits with a resolution of 1/4 bit
(or 1/8 C8i clock cycle) when the input data rate is
16.384Mb/s. When the input data rate is 32.768Mb/s,
the possible adjustment is up to 7 1/2 bits with a
resolution of 1/2 bit (or 1/8 C8i clock cycle). Figures
10, 11 and 12 describe the details of the input bit
delay programming for the local and the backplane
interfaces respectively.
Bit 0
Bit 0
Bit 7 Bit 6
Bit 7
Bit 7 Bit 6
Bit 7
Bit 7 Bit 6
Bit 7
Bit 5
Bit 7
Bit 5
Bit 6
Bit 4
Bit 5
Bit 6
Bit 4
Ch0
Bit 5
Ch0
Bit 6
Ch0
Bit 3 Bit 2
Bit 4
Ch0
Bit 6
Bit 3
Ch0
Bit 4
Advance Information
Ch0
Bit 5
Ch0
Bit 3
Ch0
Bit 2
Bit 5
Bit 3
Bit 1
Bit 2
Bit 5
Bit 1
Bit 2
Bit 5
Bit 4
Bit 0
Bit 1
Bit 4
Bit 0
Bit 1
Bit 4
Bit 0
Bit 4
Bit 0