MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 26

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

MT90868
26
overflow, the internal BER counter will stop updating
the error count when the error count reaches
0xFFFF. In additional to the BER registers, the
CBERL bit and the CBERB bit of the Control
Register are used to clear the backplane and the
local bit error count registers; the SBERB and
SBERL are used to enable the backplane and the
local BER transmitters and receivers. See Table 24,
25, 26, 27, 28 and 29 for the detailed descriptions of
the BER registers.
The BER test should be carried out as follows:
•
•
•
Device Initialization
The RESET pin is a synchronous system reset signal
that puts the MT90868 into its reset state. When
RESET goes low, it disables the LSTo0-63 and
LCSTo0-3 outputs and drives the BSTo0-63 outputs
to high. It also clears the internal device registers
and the internal counters. See Figure 25 for the reset
timing.
Upon powering up, the MT90868 must be initialized
according to the following initialization sequences:
• Set the ODE pin to low to tristate the LSTo0- 63,
LCSTo0-3 and BSTo0-63 outputs.
Set the SBERB and the SBERL bits to zero to
disable the backplane and the local BER
transmitters during the programming of the
backplane and local connection memories for the
BER test; when the BER transmitters are
disabled, the transmitter outputs are set to zero,
Set the SBERB and SBERL bit from zero to one
to enable the BER transmitters and receivers
upon the completion of the programming of the
connection memories,
Allow the BER transmitters and receivers to run
for at least two frames (or the delay between the
serial data output and the serial date input)
before the BER receivers can correctly identify
errors in the BER pattern but ignore the error
BSTo 0, 2,
BSTo 1, 3,
Figure 17 - Backplane Output Streams Availability for BER Test at 32Mb/s mode
4, 6,
5, 7,
8, 10,
9, 11,
To enable the bit error rate test for the unshaded channels,
one of the shaded channels on their right hand side has to be enabled.
Example: To enable Ch8 for BER test mode, Ch10 or Ch11 has to be enabled.
The bit error rate test mode is available for the shaded channels.
12,
13,
... ,
... ,
56, 58, 60,
57, 59, 61,
62.
63.
•
•
•
•
(Note : The transmitter and receiver for both local
and
independently to each other.)
When the backplane port is in the 32Mb/s mode, the
bit error rate test mode is not available for the
backplane output streams
mode. Figure 17 explains the details. When the
backplane port is in the 16Mb/s mode, all backplane
output streams are available.
•
•
•
•
4n
4n
+
+
counts displayed in the BER count registers
during this training period,
After the training period, clear the BER count
registers by setting the CBERL and the CBERB
bit of the control register from zero to one,
Set the CBERL and CBERB bits from one to
zero to release the BER counter; the BER
receivers receive the BER sequence and perform
the comparison,
Record the bit errors by reading the BER count
registers upon the completion of the BER test,
Clear the BER counters by setting the CBERB
and CBERL from zero to one upon the
completion of the BER test,
Set the TRST pin to low to disable the internal
JTAG TAP controller,
Set RESET pin to low to reset the device, To
ensure proper reset action, the reset pin must be
held low for longer than 500ns. A delay of 100 s
must
microprocessor access is performed after the
RESET pin is set high, this delay is required for
the initialization of the APLL.
Use the Block Programming mode as described
in the Memory Block Programming section to
initialize the local and the backplane connection
memories,
Set the ODE pin to high after the connection
memories are programmed to release the
0
3
,
backplane
(for
4n
+
also
0 n 15
1
unless the output stream
be
interface
)
Advance Information
is enabled for the BER test
applied
BSTo0, 1, 4, 5, 8, 9,
can
before
be
controlled
the
4n
+
2
... ,
first
or