MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 22

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

MT90868
22
A15-A0
Table 3 - Address Map for Internal Registers,
004C
004D
005C
005D
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005E
005F
0060
0061
0062
0063
0064
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Local Output Channel Advancement Register 31,
LOCAR31
Local Input Bit Delay Register 0, LIDR0
Local Input Bit Delay Register 1, LIDR1
Local Input Bit Delay Register 2, LIDR2
Local Input Bit Delay Register 3, LIDR3
Local Input Bit Delay Register 4, LIDR4
Local Input Bit Delay Register 5, LIDR5
Local Input Bit Delay Register 6, LIDR6
Local Input Bit Delay Register 7, LIDR7
Local Input Bit Delay Register 8, LIDR8
Local Input Bit Delay Register 9, LIDR9
Local Input Bit Delay Register 10, LIDR10
Local Input Bit Delay Register 11, LIDR11
Local Input Bit Delay Register 12, LIDR12
Local Input Bit Delay Register 13, LIDR13
Local Input Bit Delay Register 14, LIDR14
Local Input Bit Delay Register 15, LIDR15
Local Input Bit Delay Register 16, LIDR16
Local Input Bit Delay Register 17, LIDR17
Local Input Bit Delay Register 18, LIDR18
Local Input Bit Delay Register 19, LIDR19
Local Input Bit Delay Register 20, LIDR20
Local Input Bit Delay Register 21, LIDR21
Backplane Input Bit Delay Register 0, BIDR0
Backplane Input Bit Delay Register 1, BIDR1
Backplane Input Bit Delay Register 2, BIDR2
Backplane Input Bit Delay Register 3, BIDR3
Backplane Input Bit Delay Register 4, BIDR4
Backplane Input Bit Delay Register 5, BIDR5
Backplane Input Bit Delay Register 6, BIDR6
Backplane Input Bit Delay Register 7, BIDR7
Backplane Input Bit Delay Register 8, BIDR8
Backplane Input Bit Delay Register 9, BIDR9
Backplane Input Bit Delay Register 10, BIDR10
Backplane Input Bit Delay Register 11, BIDR11
Backplane Input Bit Delay Register 12, BIDR12
when A15 = 0 (continued)
Internal Register
A15-A0
Table 3 - Address Map for Internal Registers,
006C
006D
007C
007D
7FFF
0065
0066
0067
0068
0069
006A
006B
006E
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007E
007F
0080
0081
0082
0083
0084
0085
0086
0087
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Backplane Input Bit Delay Register 13, BIDR13
Backplane Input Bit Delay Register 14, BIDR14
Backplane Input Bit Delay Register 15, BIDR15
Backplane Input Bit Delay Register 16, BIDR16
Backplane Input Bit Delay Register 17, BIDR17
Backplane Input Bit Delay Register 18, BIDR18
Backplane Input Bit Delay Register 19, BIDR19
Backplane Input Bit Delay Register 20, BIDR20
Backplane Input Bit Delay Register 21, BIDR21
Local Output Advancement Register 0, LOAR0
Local Output Advancement Register 1, LOAR1
Local Output Advancement Register 2, LOAR2
Local Output Advancement Register 3, LOAR3
Local Output Advancement Register 4, LOAR4
Local Output Advancement Register 5, LOAR5
Local Output Advancement Register 6, LOAR6
Local Output Advancement Register 7, LOAR7
Backplane Output Advancement Register 0, BOAR0
Backplane Output Advancement Register 1, BOAR1
Backplane Output Advancement Register 2, BOAR2
Backplane Output Advancement Register 3, BOAR3
Backplane Output Advancement Register 4, BOAR4
Backplane Output Advancement Register 5, BOAR5
Backplane Output Advancement Register 6, BOAR6
Backplane Output Advancement Register 7, BOAR7
Backplane Data Input Selection Register, BDISR
Backplane Data Memory Read Selection Register,
BDMRSR
Local Data Memory Read Selection Register, LDMRSR
Local BER Start Receive Register, LBSRR
Local BER Length Register, LBLR
Local BER Count Register, LBCR
Backplane BER Start Receive Register, BBSRR
Backplane BER Length Register, BBLR
Backplane BER Count Register, BBCR
Reserved
Reserved
when A15 = 0 (continued)
Internal Register
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