MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet - Page 9

• Manufacturer Part Number: MT90868
• Description: High Bandwidth Digital Switch - 8,192 x 8,192 channels among local streams and 1,024 x 1,024 channels among two selected backplane streams
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Pin Description (continued)
AE14, AD11, AD12, AD13,
AC9, AC11, AD10, AC10,
AD9, AC14, AC13, AD14,
AF15, AE15, AC15, AD15.
AF16, AE16, AD16, AC16,
AF17, AE17, AD17, AC17,
AF18, AE18, AD18, AC18,
AF19, AE19, AD19, AC19.
PBGA Ball Number
AE13
AE11
AE21
AE20
AF13
AF12
AF11
AF14
AF21
AF20
B12
A12
A11
CLKBYPS
D0 - D15
A0 - A15
Name
TMS
TM1
TM2
SG1
R/W
DTA
TCK
AT1
DT1
TDi
CS
DS
APLL Bypass clock (5V Tolerant Input): This pin accepts a
131.072MHz clock for device testing purpose. In normal
operation, this input MUST be low.
APLL Test Pin 1 (3.3V Tolerant Input): Used for APLL testing
only. In normal operation, this input MUST be low.
APLL Test Pin 2 (3.3V Tolerant Input): Used for APLL testing
only. In normal operation, this input MUST be low.
APLL Test Control (3.3V Tolerant Input): Used for APLL
testing only. In normal operation, this input MUST be low.
Analog Test Access (3.3V Tolerant I/O): Used for APLL
testing only. This pin is pulled low by an internal pull-down
resistor. No connection for normal operation.
Digital Test Access (3.3V Output): Used for APLL testing
only. No connect for normal operation.
Chip Select (5V Tolerant Input): Active low input used by the
microprocessor to enable the microprocessor port access.
Data Strobe (5V Tolerant Input): This active low input works
in conjunction with CS to enable the microprocessor port read
and write operations.
Read/Write (5V Tolerant Input): This input controls the
direction
microprocessor access.
Address 0 - 15 (5V Tolerant Inputs): These pins form the 16-
bit address bus of the microprocessor port.
Data Bus 0 - 15 (5V Tolerant I/Os): These pins form the 16-bit
data bus of the microprocessor port.
Data Transfer Acknowledgment (5V Tolerant Output): This
active low output indicates that a data bus transfer is complete.
A pull-up resistor is required to hold at HIGH level.
Test Mode Select (5V Tolerant Input with internal pull-up):
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up resistor
when it is not driven.
Test Clock (5V Tolerant Input): Provides the clock to the
JTAG test logic.
Test Serial Data In (5V Input with internal pull-up): JTAG
serial test instructions and data are shifted in on this pin. This
pin is pulled high by an internal pull-up resistor when it is not
driven.
of
the
data
Description
bus
lines
(D0-D15)
MT90868
during
a
9