CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 23

• Manufacturer Part Number: CYNCP80192
• Description: Network Database Coprocessor
• Manufacturer: Cypress Semiconductor

8.0
On power-up (boot), the network processor will apply the following sequence of operations.
Hardware Interface Timing Protocols—NDC Interface. The network processor interface of the NDC supports a variety of
SSRAM interfaces. It supports both SyncBurst as well as ZBT SSRAMs. IFC_CFG[2:0] pins select the interface type for the device
as follows. (Refer to SSRAM specifications and application notes from such vendors as IDT and Micron.)
Document #: 38-02043 Rev. *B
1. Write SRST and CFG information to 1 in the CFG register.
2. Wait at least 32 cycles, then poll on SRST.
3. Write the CFG registers to each of the NSEs, starting with the one residing at the least significant address.
4. Write the CFG registers of the last NSE in the depth-cascaded system, setting the LDEV and LRAM bits to a 1.
5. The descriptor block is now Ready for use by the network processor(s) for building, managing, and/or searching the database.
000: ZBT pipelined mode
001: ZBT flowthrough mode
010: SyncBurst pipelined mode (early Write)
011: SyncBurst pipelined mode (late Write)
100–111: Reserved.
NDC Subsystem Power-up Initialization Procedure
CYNCP80192
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