CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 6

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CYNCP80192

Manufacturer Part Number
CYNCP80192
Description
Network Database Coprocessor
Manufacturer
Cypress Semiconductor
Datasheet

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2.0
The CYNPC80192 NDC contains the following function blocks, shown in Figure 2-1.
Note:
Document #: 38-02043 Rev. *B
1.
• The hardware interface to the NDC uses an SSRAM interface. The CYNCP80192 device supports ZBT
• All instructions and/or responses are mapped into the SSRAM address (ADR) space.
• The CYNCP80192 device provides simultaneous multiple layer, variable-width tables (×68, ×136, ×272).
• There is support for table sizes up to four million ×34 entries.
• There are 33 million searches per second (Msps) in the ×68 configuration (CFG).
• The CYNCP80192 device is compatible with 1-Mb, 2-Mb, and 4-Mb NSEs.
• It has a glueless interface to industry standard synchronous SRAMs and NSEs.
• The CYNCP80192 device uses up to 100 MHz master clock frequency.
• It has an IEEE 1149.1 test access port.
• There is a 2.5V/3.3V power supply and a 388-pin BGA package.
ZBT flowthrough, and SyncBurst
1. The device can be configured for returning SADR or SDATA.
Network
Processor
Interface
(SSRAM bus)
Features
Configuration
Operating
Register
Register
pipelined (late and early write) types of SSRAMs.
Figure 2-1. CYNCP80192 Block Diagram
Return ID
Data
Conversion Controller
Management, and
Pipeline and Table
Bus Protocol
SSRAM Interface
Associative
Interface
NSE
SDATA
[1]
SADR
CYNCP80192
[1]
SSRAMs
NSE
pipelined,
Page 6 of 42

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