CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 25

• Manufacturer Part Number: CYNCP80192
• Description: Network Database Coprocessor
• Manufacturer: Cypress Semiconductor

10.0
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data
is sampled one cycle later; for Read cycles, the data is available to the processor one cycle later. Both Write- and Read-cycle
latency is one cycle, and there is no gap required between Read and Write operation. Every cycle is available for the network
processor(s) for full utilization of the bus bandwidth. See Figure 10-1. Note. BWE_L is not used in this mode and should be tied
inactive.
Document #: 38-02043 Rev. *B
DATA[63:0]
BW_L[7:0]
CPID[7:0]
ADR[9:0]
CE2_L
R/W_L
STRB
CE_L
CE_2
CLK
ZBT Flowthrough SSRAM Interface Mode
1
Write
A1
Figure 10-1. ZBT Flowthrough SSRAM Interface (Mode 001)
2
Read
A2
D1
3
Write
Q2
A3
4
Write
A4
D3
CPID
5
Read
A5
Q4
6
Q5
CYNCP80192
7
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