CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 30

• Manufacturer Part Number: CYNCP80192
• Description: Network Database Coprocessor
• Manufacturer: Cypress Semiconductor

15.0
The CYNPC80192 supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG Standard
1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L.
Table 15-1 and Table 15-2 describe the operations that the test access port controller supports and the test access port device
ID register.
Table 15-1. Test Access Port Controller Instructions
Table 15-2. Test Access Port Device ID Register
Document #: 38-02043 Rev. *B
SAMPLE/PRELOAD Mandatory Sample/Preload. Loads the values of signals going to and from I/O pins into the boundary
Part Number [27:12] 0000 0000 0000 0011 This is the part number for this device.
Revision
Field
MFID
Instruction
LSB
EXTEST
INTEST
JTAG (1149.1) Testing
Range
[31:28]
[11:1]
0
Mandatory External Test. Uses boundary scan values shifted in from TAP to test connectivity external to
Optional Internal Test. Allows slow-speed functional testing of the device using the boundary scan
Type
000_1101_1100
Initial Value
0001
scan shift register to provide a snapshot of the normal functional operation.
the device.
register to provide the I/O values.
1
Revision Number. This is the current device revision number. Numbers start
from one and increment by one for each revision of the device.
Manufacturer ID. This field is the same as the manufacturer ID used in the TAP
controller.
Least Significant Bit.
Description
Description
CYNCP80192
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