CYNCP80192 Cypress Semiconductor, CYNCP80192 Datasheet - Page 24

• Manufacturer Part Number: CYNCP80192
• Description: Network Database Coprocessor
• Manufacturer: Cypress Semiconductor

9.0
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data
is sampled two cycles later; for Read cycles, the data is available to the processor two cycles later. Both Write- and Read-cycle
latency is two cycles and there is no gap required between Read and Write operations. Every cycle is available for the network
processor(s) for full utilization of the bus bandwidth. See Figure 9-1. Note. BWE_L is not used in this mode and should be tied
inactive.
Document #: 38-02043 Rev. *B
DATA[63:0]
BW_L[7:0]
CPID[7:0]
ADR[9:0]
R/W_L
STRB
CE_L
CE_2
CLK
ZBT Pipelined SSRAM Interface Mode
1
Write
A1
Figure 9-1. ZBT Pipelined SRAM Interface (Mode 000)
2
Read
A2
3
Write
A3
D1
4
Write
Q2
A4
CPID
5
Read
A5
D3
6
Read
D4
A6
CYNCP80192
7
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