ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 136
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ds26524
Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS26524.pdf
(273 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for T1 mode. See T1RSLC2.
Bit 7: International Bit (Si).
Bit 6: Frame Non-Alignment Signal Bit (1).
Bit 5: Remote Alarm (A).
Bit 4: Additional Bit 4 (Sa4).
Bit 3: Additional Bit 5 (Sa5).
Bit 2: Additional Bit 6 (Sa6).
Bit 1: Additional Bit 7 (Sa7).
Bit 0: Additional Bit 8 (Sa8).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for T1 mode. See T1RSLC3.
Bit 7: Si Bit of Frame 14 (SiF14).
Bit 6: Si Bit of Frame 12 (SiF12).
Bit 5: Si Bit of Frame 10 (SiF10).
Bit 4: Si Bit of Frame 8 (SiF8).
Bit 3: Si Bit of Frame 6 (SiF6).
Bit 2: Si Bit of Frame 4 (SiF4).
Bit 1: Si Bit of Frame 2 (SiF2).
Bit 0: Si Bit of Frame 0 (SiF0).
SiF14
Si
7
0
7
0
E1RNAF (E1 Mode)
E1 Receive Non-Align Frame Register
065h + (200h x n): where n = 0 to 3, for Ports 1 to 4
E1RSiAF (E1 Mode)
E1 Received Si Bits of the Align Frame Register
066h + (200h x n): where n = 0 to 3, for Ports 1 to 4
SiF12
6
1
0
6
0
SiF10
A
5
0
5
0
136 of 273
SiF8
Sa4
0
0
4
4
SiF6
Sa5
3
0
3
0
SiF4
Sa6
2
0
2
0
SiF2
Sa7
1
0
1
0
SiF0
Sa8
0
0
0
0
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