ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 178

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive Channel Blocking Control Bits for Channels 1 to 32 (CH[1:32]).
*Note that RCBR4 has two functions:
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Setting any of the CH[1:24] bits in the RSI1:RSI3 registers causes signaling data to be reinserted for the associated
channel. RSI4 is used for 2.048MHz backplane operation.
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking
signal for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the
RCHBLK signal will pulse high during the F-Bit time. In this mode, RCBR4.1:RCBR4.7 should be set to 0.
CH16
CH24
CH32
CH8
CH16
CH24
CH32
CH8
7
0
7
0
RCBR4.0 = 0, do not pulse RCHBLK during the F-bit.
RCBR4.0 = 1, pulse RCHBLK during the F-bit.
CH15
CH23
CH31
CH7
CH15
CH23
CH31
CH7
RCBR1, RCBR2, RCBR3, RCBR4
Receive Channel Blocking Registers 1 to 4
0C4h, 0C5h, 0C6h, 0C7h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RSI1, RSI2, RSI3, RSI4
Receive-Signaling Reinsertion Enable Registers 1 to 4
0C8h, 0C9h, 0CAh, 0CBh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
0
6
0
CH14
CH22
CH30
CH6
CH14
CH22
CH30
CH6
5
0
5
0
CH13
CH21
CH29
CH5
CH13
CH21
CH29
CH5
4
0
4
0
178 of 273
CH12
CH20
CH28
CH4
CH12
CH20
CH28
CH4
3
0
3
0
CH11
CH19
CH27
CH3
CH11
CH19
CH27
CH3
2
0
2
0
CH10
CH18
CH26
CH2
CH10
CH18
CH26
CH2
1
0
1
0
(F-bit)
CH17
CH25
CH1
CH9
CH17
CH25
CH1
CH9
0
0
0
0
RCBR1
RCBR2
RCBR3
RCBR4*
(E1 Mode
Only)
RSI1
RSI2
RSI3
RSI4
(E1 Mode
Only)