ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 153
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ds26524
Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS26524.pdf
(273 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being
used.
Bit 6: Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
Bit 5: Receive Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used.
Bit 4: Receive Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used.
Bit 3: Receive Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used.
Bit 2: Receive Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used.
Bit 1: Receive Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used.
Bit 0: Receive Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being
used.
BPBSE8
7
0
BPBSE7
RBPBS
Receive BERT Port Bit Suppress Register
08Bh + (200h x n): where n = 0 to 3, for Ports 1 to 4
6
0
BPBSE6
5
0
BPBSE5
153 of 273
4
0
BPBSE4
3
0
BPBSE3
2
0
BPBSE2
1
0
BPBSE1
0
0
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