upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 121

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upd78f0124m6gba1-8et

Manufacturer Part Number
upd78f0124m6gba1-8et
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
f
MCC = 1
XP
Notes 1.
: Oscillation stopped
CPU clock: f
f
R
CPU clock: f
: Oscillating
f
CSS = 1
Status 5
f
XP
R
: Oscillating
: Oscillating
Status 4
2.
3.
4.
5.
MCC = 0
Note 4
XT
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using the internal oscillation clock even in STOP mode if “Internal
oscillator cannot be stopped” is selected by a mask option. Internal oscillation clock division can be
selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1
interrupt request before watchdog timer overflow. If this processing is not performed, an internal
reset signal is generated at watchdog timer overflow after STOP instruction execution.
The operation cannot be shifted between subsystem clock operation and internal oscillation clock
operation.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
(4) When “Internal oscillator cannot be stopped” is selected by mask option
XT
CSS = 0
CPU clock: f
f
f
XP
R
: Oscillating
: Oscillating
Status 3
HALT instruction
Note 4
HALT instruction
Figure 5-13. Status Transition Diagram (4/4)
XP
Interrupt
instruction
Interrupt
Interrupt
STOP
CHAPTER 5 CLOCK GENERATOR
(when subsystem clock is used)
MCM0 = 1
MCM0 = 0
User’s Manual U16315EJ3V1UD
Interrupt
HALT
instruction
Note 1
instruction
Interrupt
STOP
f
CPU clock: f
f
XP
R
STOP
: Oscillating
: Oscillating
Status 2
HALT
Note 3
Interrupt
HALT
instruction
R
Interrupt
instruction
MSTOP = 1
MSTOP = 0
STOP
Reset release
HALT instruction
Interrupt
Note 2
f
XP
: Oscillation stopped
Reset
CPU clock: f
f
R
: Oscillating
Status 1
Note 5
R
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