upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 536

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

536
Standby
function
Reset
function
Clock
monitor
Power-on-
clear
circuit
(POC)
Function
OSTS:
Oscillation
stabilization
time select
register
STOP mode
setting and
operating
statuses
Timing of reset
due to
watchdog timer
overflow
RESF: Reset
control flag
register
CLM: Clock
monitor mode
register
Power-on-clear
circuit functions
Cautions for
power-on-clear
circuit
Details of
Function
−
To set the STOP mode while the X1 input clock is used as the CPU clock, set
OSTS before executing the STOP instruction.
Before setting OSTS, confirm with OSTC that the desired oscillation stabilization
time has elapsed.
If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
Because the interrupt request signal is used to release the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately released if set. Thus, the STOP mode is
reset to the HALT mode immediately after execution of the STOP instruction and
the system returns to the operating mode as soon as the wait time set using the
oscillation stabilization time select register (OSTS) has elapsed.
For an external reset, input a low level for 10
During reset input, the X1 input clock and internal oscillation clock stop oscillating. p. 360
When the STOP mode is released by a reset, the STOP mode contents are held
during reset input. However, the port pins become high-impedance, except for
P130, which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or
the internal reset signal.
If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1
(CLMRF) of the reset control flag register (RESF) is set to 1.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
by OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U16315EJ3V1UD
Cautions
POC
DD
) fluctuates for a certain period in the
), the system may be repeatedly reset
µ
s or more to the RESET pin.
p. 350
p. 350
p. 350
p. 350
p. 356
p. 360
p. 360
p. 361
p. 362
p. 366
p. 368
p. 368
p. 374
p. 376
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