upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 333

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon RESET input.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Cautions 1. Be sure to clear bit 7 of IF1L to 0.
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
Address: FFE1H
Symbol
IF0H
Address: FFE2H
Symbol
IF1L
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
3. Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the
TMIF010
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0 = 0;” and
“_asm(“clr1 IF0L, 0”);” should be used when describing in C language, because assembly
instructions after compilation must be 1-bit memory manipulation instructions (CLR1).
If an 8-bit memory manipulation instruction “IF0L & = 0xfe;” is described in C language, for
example, it is converted to the following three assembly instructions after compilation:
In this case, at the timing between “mov a, IF0L” and “mov IF0L, a”, if the request flag of
another bit of the identical interrupt request flag register (IF0L) is set to 1, it is cleared to 0
by “mov IF0L, a”.
manipulation instruction in C language.
SREIF6
Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
XXIFX
<7>
<7>
mov a, IF0L
and
mov IF0L, a
7
0
0
1
After reset: 00H
After reset: 00H
a, #0FEH
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
TMIF000
PIF5
PIF6
<6>
<6>
6
CHAPTER 16 INTERRUPT FUNCTIONS
R/W
R/W
Therefore, care must be exercised when using an 8-bit memory
TMIF50
WTIF
PIF4
<5>
<5>
<5>
User’s Manual U16315EJ3V1UD
TMIFH0
KRIF
PIF3
<4>
<4>
<4>
Interrupt request flag
TMIFH1
TMIF51
PIF2
<3>
<3>
<3>
DUALIF0
WTIIF
PIF1
<2>
<2>
<2>
STIF6
SRIF0
PIF0
<1>
<1>
<1>
SRIF6
LVIIF
ADIF
<0>
<0>
<0>
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