upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 129

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

5.8.5 Register settings
Notes 1.
X1 input clock
Internal oscillation
clock
Subsystem
clock
The table below shows the statuses of the setting flags and status flags when each mode is set.
Note 4
f
2.
3.
4.
5.
6.
CPU
Valid only when “Can be stopped by software” is selected for the internal oscillator by a mask option.
Do not set MCC = 1 or MSTOP = 1 during X1 input clock operation (even if MCC = 1 or MSTOP = 1 is set,
the X1 oscillation does not stop).
Do not set MCC = 1 during internal oscillation clock operation (even if MCC = 1 is set, the X1 oscillation
does not stop). To stop X1 oscillation during internal oscillation clock operation, use MSTOP.
Shifting to subsystem clock operation mode must be performed from the X1 input clock operation mode.
From subsystem clock operation mode, only X1 input clock operation mode can be shifted to.
Do not set MCM0 = 0 (shifting to internal oscillation clock operation) during subsystem clock operation.
Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, X1 oscillation does
not stop). To stop X1 oscillation during subsystem clock operation, use MCC.
Note 2
Internal oscillator oscillating
Internal oscillator stopped
X1 oscillating
X1 stopped
X1 oscillating, internal oscillator oscillating
X1 stopped, internal oscillator oscillating
X1 oscillating, internal oscillator stopped
X1 stopped, internal oscillator stopped
Mode
Table 5-7. Clock and Register Setting
CHAPTER 5 CLOCK GENERATOR
User’s Manual U16315EJ3V1UD
MCC
0
PCC Register
Note 3
0
0
0
0
1
0
1
CSS
0
0
0
1
1
1
1
0
Setting Flag
Register
MCM0
MCM
1
1
1
1
Note 5
Note 5
Note 5
Note 5
1
1
0
0
Register
MSTOP RSTOP
MOC
0
0
0
0
Note 6
Note 6
Note 6
Note 6
0
0
0
1
Register
RCM
0
1
0
0
0
0
1
1
Note 1
Register
PCC
CLS
Status Flag
0
0
0
0
1
1
1
1
Register
MCM
MCS
1
1
0
0
1
1
1
1
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