upd78f0124m6gba1-8et Renesas Electronics Corporation., upd78f0124m6gba1-8et Datasheet - Page 231

• Manufacturer Part Number: upd78f0124m6gba1-8et
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

11.3 Registers Controlling Clock Output Controller
The following two registers are used to control the clock output controller.
• Clock output selection register (CKS)
• Port mode register 14 (PM14)
(1) Clock output selection register (CKS)
Note Set the output clock to satisfy the following condition.
Remarks 1. f
Address: FF40H
Symbol
CKS
This register sets output enable/disable for clock output (PCL) and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CKS to 00H.
• Output clock ≤ 10 MHz
2. f
3. Figures in parentheses are for operation with f
X
XT
CLOE
CCS3
: X1 input clock oscillation frequency
: Subsystem clock oscillation frequency
7
0
0
1
0
0
0
0
0
0
0
0
1
After reset: 00H
Figure 11-2. Format of Clock Output Selection Register (CKS)
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
CCS2
Other than above
6
0
0
0
0
0
1
1
1
1
0
CHAPTER 11 CLOCK OUTPUT CONTROLLER
R/W
CCS1
User’s Manual U16315EJ3V1UD
5
0
0
0
1
1
0
0
1
1
0
PCL output enable/disable specification
CLOE
CCS0
<4>
0
1
0
1
0
1
0
1
0
X
f
f
f
f
f
f
f
f
f
Setting prohibited
X
X
X
X
X
X
X
X
XT
= 10 MHz or f
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
(10 MHz)
CCS3
(32.768 kHz)
2
3
4
5
6
7
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.125 kHz)
3
PCL output clock selection
XT
CCS2
2
= 32.768 kHz.
CCS1
1
Note
CCS0
0
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