upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 236

• Manufacturer Part Number: upd78f0134hgka1-9et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) Watchdog timer enable register (WDTE)
236
Address: FF99H
Symbol
WDTE
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 9AH.
Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM
Remarks 1. f
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If
7
After reset: 9AH
2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “internal oscillator cannot be
3. After reset is released, WDTM can be written only once by an 8-bit memory
4. WDTM cannot be set by a 1-bit memory manipulation instruction.
5. If “internal oscillator can be stopped by software” is selected by the option byte and
2. f
3.
4. Figures in parentheses apply to operation at f
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
Figure 10-3. Format of Watchdog Timer Enable Register (WDTE)
R
XP
when the CPU is operating on the subsystem clock and the high-speed system clock
is stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
stopped” is selected by the option byte, other values are ignored).
manipulation instruction. If writing attempted a second time, an internal reset signal
is generated. If the source clock to the watchdog timer is stopped, however, an
internal reset signal is generated when the source clock to the watchdog timer
resumes operation.
the watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not
resume operation even if WDCS4 is cleared to 0. In addition, the internal reset signal
is not generated.
the source clock to the watchdog timer is stopped, however, an internal reset signal
is generated when the source clock to the watchdog timer resumes operation.
signal is generated. If the source clock to the watchdog timer is stopped, however,
an internal reset signal is generated when the source clock to the watchdog timer
resumes operation.
: Don’t care
: Internal oscillation clock oscillation frequency
: High-speed system clock oscillation frequency
6
R/W
5
CHAPTER 10 WATCHDOG TIMER
User’s Manual U16899EJ3V0UD
4
3
R
= 480 kHz (MAX.), f
2
1
XP
= 10 MHz
0