upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 564

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upd78f0134hgka1-9et-a

Manufacturer Part Number
upd78f0134hgka1-9et-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
E.2 Revision History up to Previous Edition
each edition in which the revision was applied.
564
2nd edition
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
Edition
Addition of PD78F0138HF1-BA2, 78F0138HDGK-8A8, and 78F0138HDF1-BA2 to 1.3
Ordering Information
Modification of 1.5 Kx1 Series Lineup
Modification of recommended connection for unused RESET pin in Table 2-2. Pin I/O
Circuit Types
Addition of Cautions 1 and 2 to Figure 5-7 Format of Oscillation Stabilization Time
Select Register (OSTS)
Deletion of (7) System wait control register (VSWC) in 5.3 Registers Controlling
Clock Generator
Addition of description for when used as capture register to Interrupt request generation
column in Figure 6-6 Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Addition of description for when used as capture register to Interrupt request generation
column in Figure 6-7 Format of 16-Bit Timer Mode Control Register 01 (TMC01)
Modification of Note 1 and correction of Cautions 4 and 5 in Figure 6-12 Format of
Prescaler Mode Register 00 (PRM00)
Modification of Note 1 and correction of Cautions 4 and 5 in Figure 6-13 Format of
Prescaler Mode Register 01 (PRM01)
Modification of Note in Figure 7-5. Format of Timer Clock Selection Register 50
(TCL50)
Modification of Note in Figure 7-6. Format of Timer Clock Selection Register 51
(TCL51)
Modification of Note 1 in Figure 8-5. Format of 8-Bit Timer H Mode Register 0
(TMHMD0)
Modification of Note in Figure 8-6. Format of 8-Bit Timer H Mode Register 1
(TMHMD1)
Correction of Table 10-1 Loop Detection Time of Watchdog Timer
Addition of Note to Figure 11-2 Format of Clock Output Selection Register (CKS)
Modification of Note 1 in Figure 13-4 Format of Baud Rate Generator Control
Register 0 (BRGC0)
Modification of Note 1 in Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
Modification of (h) SBF transmission in 14.4.2 Asynchronous serial interface (UART)
mode
Modification of Note in Figure 15-5 Format of Serial Clock Selection Register 10
(CSIC10)
Modification of Note in Figure 15-6 Format of Serial Clock Selection Register 11
(CSIC11)
APPENDIX E REVISION HISTORY
User’s Manual U16899EJ3V0UD
Description
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 16-BIT
TIMER/EVENT
COUNTER 00 AND 01
CHAPTER 7 8-BIT
TIMER/EVENT
COUNTERS 50 AND 51
CHAPTER 8 8-BIT
TIMERS H0 AND H1
CHAPTER 10
WATCHDOG TIMER
CHAPTER 11 CLOCK
OUTPUT/BUZZER
OUTPUT
CONTROLLER
CHAPTER 13 SERIAL
INTERFACE UART0
CHAPTER 14 SERIAL
INTERFACE UART6
CHAPTER 15 SERIAL
INTERFACES CSI10
AND CSI11
Applied to:
(1/2)

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