upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 411

• Manufacturer Part Number: upd78f0134hgka1-9et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

23.3 Registers Controlling Low-Voltage Detector
(1) Low-voltage detection register (LVIM)
The low-voltage detector is controlled by the following registers.
Address: FFBEH
Symbol
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
LVIM
A reset other than LVI clears LVIM to 00H.
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Notes 1.
Caution To stop LVI, follow either of the procedures below.
LVION
LVIMD
LVIF
LVION
<7>
0
1
0
1
0
1
4
Note 5
Notes 3,
Note 3
2.
3.
4.
5.
After reset: 00H
Bit 0 is read-only.
Bit 4 may be 0 or 1. This bit corresponds to the LVIE bit in the 78K0/KE1.
LVION and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are
not cleared to 0 in the case of an LVI reset.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
When using 8-bit manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVION to 0.
Disables operation
Enables operation
Generates interrupt signal when supply voltage (V
Generates internal reset signal when supply voltage (V
Supply voltage (V
Supply voltage (V
Figure 23-2. Format of Low-Voltage Detection Register (LVIM)
6
0
CHAPTER 23 LOW-VOLTAGE DETECTOR
R/W
DD
DD
5
0
)
) < detection voltage (V
Note 1
Low-voltage detection operation mode selection
detection voltage (V
User’s Manual U16899EJ3V0UD
Enables low-voltage detection operation
0
Note 2
4
Low-voltage detection flag
LVI
LVI
3
0
), or when operation is disabled
)
DD
) < detection voltage (V
DD
) < detection voltage (V
2
0
LVIMD
<1>
LVI
)
LVI
LVIF
<0>
)
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