st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 105

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st20-gp6

Manufacturer Part Number
st20-gp6
Description
Gps Processor
Manufacturer
STMicroelectronics
Datasheet
Notes
Analogue specifications
LowPowerClockIn and LowPowerClockOsc analogue pins are dedicated low power pins and
should only be connected as in Figure 13.1 on page 74. Due to their high impedance, they must
not be monitored or loaded by test equipment.
AC specifications
Notes
Symbol
t
t
vddr
vddf
1
2
3
4
5
1
2
This is the static specification to ensure low current.
Output load of 2mA on all pins except PIO. Output load of 4mA on PIO.
Excludes power used to drive external loads. Includes operation of the 32 KHz watch crys-
tal oscillator.
Device operation suspended by use of the low power controller with VDD and RTCVDD
within specification. Frequency of system clock (fclk) is 16.368 MHz and frequency of low
power clock is 32768 Hz.
With RTCVDD at 2.4 V and VDD at 0 V. All inputs static except LowPowerClockIn and
LowPowerClockOsc, frequency of low power clock 32768 Hz. All other inputs must be in
the range -0.1 to 0.1 V.
The maximum is only a guideline to ensure a low current consumption during the change in
VDD.
The transition need not be monotonic, providing that the notRST pin is forced low during
the whole period while the main VDD voltage is not within limits set in the DC operating
conditions.
Parameter
Rise time of VDD during power up (measured
between 0.3 V and 2.7 V).
Fall time of VDD during power down (measured
between 2.7 V and 0.3 V).
Table 18.4 AC Specification
Min
5 ns
5 ns
Typical
Max
100 ms
100 ms
Units
ST20-GP6
Notes
1, 2
1, 2
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