st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 82

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
15 UART interface (ASC)
The UART interface, also referred to as the Asynchronous Serial Controller (ASC), provides serial
communication between the ST20-GP6 and other microcontrollers, microprocessors or external
peripherals.
The ASC supports full-duplex asynchronous communication. Eight or nine bit data transfer, parity
generation, and the number of stop bits are programmable. Parity, framing, and overrun error
detection are provided to increase the reliability of data transfers. Transmission and reception of
data can simply be double-buffered, or16-deep fifos may be used. For multiprocessor communica-
tions, a mechanism to distinguish the address from the data bytes is included. Testing is supported
by a loop-back option. A 16-bit baud rate generator provides the ASC with a separate serial clock
signal.
15.1 Functionality
The ASC supports full-duplex asynchronous communication, where both the transmitter and the
receiver use the same data frame format and the same baud rate. Data is transmitted on the TXD
pin and received on the RXD pin.
Data frames
8-bit data frames either consist of:
Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even
parity bit will be set, if the modulo-2-sum of the seven data bits is 1. An odd parity bit will be cleared
in this case.
9-bit data frames either consist of:
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eight data bits D0-7 (by setting the Mode bit field to 001);
seven data bits D0-6 plus an automatically generated parity bit (by setting the Mode bit field
to 011).
nine data bits D0-8 (by setting the Mode bit field to 100);
eight data bits D0-7 plus an automatically generated parity bit (by setting the Mode bit field
to 111);
eight data bits D0-7 plus a wake-up bit (by setting the Mode bit field to 101).
start
bit
(LSB)
D0
D1
D2
Figure 15.1 8-bit data frames
D3
D4
D5
D6
Data bit (D7)
Parity bit
8th
bit
stop
1st
bit
stop
2nd
bit