st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 60

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
10.3 MemWait
The MemWait pin is sampled on each processor clock cycle during accesses to banks. In cycles
when it is sampled high, the external access is halted and the strobe state does not change.
MemWait suspends the state of the EMI in the cycle after it is sampled high. The state remains
suspended until MemWait is sampled low. Any strobe edges scheduled to occur in the cycle after
MemWait is sampled will not occur. Strobe edges scheduled to occur on the same edge as
MemWait is sampled are not affected. Figure 10.3 and Figure 10.4 show the extension of the
external memory cycle and the delaying of strobe transitions. Note, the clock shown in the figures
is the internal on-chip clock and is provided as a guide to show the minimum setup time of
MemWait relative to the strobes.
Note that MemWait is ignored if it is sampled high on the last cycle of the access.
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Name
AccessTime
BusRelease-
Time
DataDriveDelay
CEe1Time
CEe2Time
OEe1Time
OEe2Time
BEe1Time
BEe2Time
LatchPoint
Programmable value
2 cycles + 0 to 15 cycles
0 to 3 cycles
0 to 7 phases after start of access cycle
Falling edge of CE: 0 to 3 phases after start of access
cycle
Rising edge of CE: 0 to 3 phases before end of access
cycle
Falling edge of OE: 0 to 3 phases after start of access
cycle
Rising edge of OE: 0 to 3 phases before end of access
cycle.
Falling edge of BE: 0 to 3 phases after start of access
cycle
Rising edge of BE: 0 to 3 phases before end of access
cycle
0 = 1 cycle before end of access cycle.
1 = end of access cycle.
Table 10.2 Parameters for generic access
16.368 MHz
122 to 1039 ns
0 to 183 ns
0 to 214 ns
0 to 92 ns
0 to 92 ns
0 to 92 ns
0 to 92 ns
0 to 92 ns
0 to 92 ns
0 to 61 ns
32.736 MHz
61 to 519 ns
0 to 92 ns
0 to 107 ns
0 to 46 ns
0 to 46 ns
0 to 46 ns
0 to 46 ns
0 to 46 ns
0 to 46 ns
0 to 30 ns