st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 76

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
The host can communicate with the DCU via a private link, using the 5 standard test pins.
Target software also has access to the diagnostic facilities and access through the DCU to the host
memory.
A logic state analyzer can be connected to the TriggerIn and TriggerOut pins. The response to
TriggerIn and the events that cause a TriggerOut signal can be controlled by the host or by target
software.
The diagnostic controller provides debugging facilities with much less impact on the software and
target performance. In particular it gives:
The connections between the diagnostic controller and other on-chip modules and external hard-
ware may vary between ST20 variants.
14.2 Access features
14.2.1 Access to target memory and peripheral registers from host
Full read and write access to the entire on-chip and external memory space is available via the
TAP. This is independent of the state of the CPU.
The DCU cannot directly access configuration registers in the on-chip peripheral space. However
this is possible via the CPU, and for this the CPU must be active with the appropriate handler
installed. Normally the DCU would initiate a trap, and the trap handler would access the appropri-
ate configuration register.
By convention, registers in the address range #20000000 to #3FFFFFFF are in the on-chip periph-
eral space and can only be accessed by the CPU. Registers and memory outside this range are
connected to the address bus and can be accessed directly by the DCU.
14.2.2 Access from target CPU process
The CPU itself can program its own diagnostic controller. Further access may be explicitly pre-
vented by the lock mechanism so that the application being debugged cannot interfere with the
breakpoint and watchpoint settings. When the breakpoint or watchpoint match occurs, then the
diagnostic controller may release the lock according to settings in the control register.
14.2.3 Access to host memory from target
If the target CPU accesses any address in the top half of the DCU memory space, then these
accesses are mapped on to host memory via the TAP as target initiated peek and poke messages.
Peek accesses and poke accesses are specifically enabled by separate property bits.
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non-intrusive attachment to the host system;
no intrusion into the performance of the CPU or any subsystems;
no intrusion into the code space, so the application builder does not need to add a debug-
ging kernel;
no intrusion into any on-chip functional modules, including any communications facilities;
no functional external connection pins are used.