st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 19

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

4
The Central Processing Unit (CPU) is the ST20 32-bit processor core. It contains instruction pro-
cessing logic, instruction and data pointers, and an operand register. It can directly access the high
speed on-chip memory, which can store data or programs. Where larger amounts of memory are
required, the processor can access memory via the External Memory Interface (EMI).
The processor provides high performance:
The scheduler provides a single level of pre-emption. In addition, multi-level pre-emption is pro-
vided by the interrupt subsystem, see Chapter 5 for details. Additionally, there is a per-priority trap
handler to improve the support for arithmetic errors and illegal instructions, refer to section 4.6.
4.1
The CPU contains six registers which are used in the execution of a sequential integer process.
The six registers are:
The Areg, Breg and Creg registers are the sources and destinations for most arithmetic and logi-
cal operations. Loading a value into the stack pushes Breg into Creg, and Areg into Breg, before
loading Areg. Storing a value from Areg, pops Breg into Areg and Creg into Breg. Creg is left
undefined.
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Central processing unit
Fast integer multiply - 4 cycle multiply
Fast bit shift - single cycle barrel shifter
Byte and part-word handling
Scheduling and interrupt support
64-bit integer arithmetic support.
Registers
The workspace pointer (Wptr) which points to an area of store where local data is kept.
The instruction pointer (Iptr) which points to the next instruction to be executed.
The status register (Status).
The Areg, Breg and Creg registers which form an evaluation stack.
Figure 4.1 Registers used in sequential integer processes
Registers
Areg
Breg
Creg
Wptr
Iptr
Local data
Program
ST20-GP6
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