cs4228a Cirrus Logic, Inc., cs4228a Datasheet - Page 25
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cs4228a
Manufacturer Part Number
cs4228a
Description
24-bit, 96 Khz Surround Sound Codec
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS4228A.pdf
(32 pages)
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5.9
DMS1:0
DDF2:0
5.10 Chip Status
CLKERR
ADCOVL
CLKERR
DCK1
7
1
X
7
Serial Port Mode
Address 0x0D
DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)
Address 0x0E
ADCOVL
DCK0
Sets the master/slave mode of the serial audio port
Clocking system status, read only
*0 -
1 -
2 -
3 -
Serial Port Data Format
0 -
1 -
2 -
3 -
*4 -
5 -
6 -
7 -
0 -
1 -
ADC overflow bit, read only
0 -
1 -
6
0
Notes: 1. All formats will default to 16 bits
X
6
DCK1:0
0
1
2
3
2. Slave mode only
3. Invalid mode
Slave (External LRCLK, SCLK)
Reserved
Reserved
Master (No 48 Fs SCLK in BRM)
Right Justified, 24-bit
Right Justified, 20-bit
Right Justified, 16-bit
Left Justified, maximum 24-bit
I
One-line Data Mode, available in BRM only
Reserved
Reserved
No Error
No MCLK is present, or a request for clock change is in progress
No overflow
ADC overflow has occurred
DMS1
2
S compatible, maximum 24-bit
5
0
5
0
BRM (Fs)
128
32 (1)
48 (2)
*64
DMS0
4
0
4
0
HRM (Fs)
RESERVED
(3)
(3)
32 (1)
64
3
0
3
0
RESERVED
DDF2
2
1
2
0
DDF1
1
0
1
0
CS4228A
DFF0
0
0
0
0
25