cs4228a Cirrus Logic, Inc., cs4228a Datasheet - Page 26

• Manufacturer Part Number: cs4228a
• Description: 24-bit, 96 Khz Surround Sound Codec
• Manufacturer: Cirrus Logic, Inc.

SDIN1, SDIN2,
SDIN3
SDOUT
SCLK
6. PIN DESCRIPTION
26
Digital Interface Power
Serial Audio Data In 3
Serial Audio Data In 2
Serial Audio Data In 1
Serial Audio Data Out
Left/Right Clock
Digital Ground
Digital Power
Master Clock
Serial Clock
SCL/CCLK SCL/CCLK
SDA/CDIN SDA/CDIN
1, 2, 3
4
5
AD0/CS
Reset
Serial Audio Data In (Input) - Two's complement MSB-first serial audio data is input on this
pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Mode Register. The options are detailed
in Figures 10, 11, 12, and 13.
Serial Audio Data Out (Output) - Two's complement MSB-first serial data is output on this
pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by
the Left/Right clock. The required relationship between the Left/Right clock, serial clock and
serial data is defined by the Serial Mode Register. The options are detailed in Figures 10,
11, 12 and 13.
The state of the SDOUT pin during reset is used to set the Control Port Mode (I
When RST is low, SDOUT is configured as an input, and the rising edge of RST latches the
state of the pin. A weak internal pull up is present such that a resistive load less than 47 kΩ
will pull the pin low, and the control port mode is I
greater than 47 kΩ during reset, the control port mode is SPI.
Serial Clock (Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins,
and out of the SDOUT pin. The pin is an output in master mode, and an input in slave
mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate
SCLK at the desired multiple of the sample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally,
or the pin can be grounded and the serial clock derived internally from MCLK.
The required relationship between the Left/Right clock, serial clock and serial audio data is
defined by the Serial Port Mode register. The options are detailed in Figures 10, 11, 12
and 13.
AD0/CS
SDOUT
SDIN3
SDIN2
SDIN1
DGND
MCLK
LRCK
SCLK
RST
VD
VL
1
1
2
2
3
4
5
5
6
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SUB
CENTER Analog Out #5, Center
SR
SL
FR
FL
AGND
VA
AINL+
AINL-
FILT
AINR-
AINR+
MUTEC
2
C. When the resistive load on SDOUT is
Analog Out #6,Subwoofer
Analog Out #4, Surround Right
Analog Out #3, Surround Left
Analog Out #2, Front Right
Analog Out #1, Front Left
Analog Ground
Analog Power
Left Channel Analog Input+
Left Channel Analog Input-
Internal Voltage Filter
Right Channel Analog Input-
Right Channel Analog Input+
Mute Control
CS4228A
2
C or SPI).